1. Field of Invention
The present invention relates to a chip package and process for forming the same. More particularly, the present invention relates to a technique for forming a chip package that combines wire-bond and flip-chip processes together.
2. Description of Related Art
In the semiconductor industry, layout diagrams of well-designed integrated circuits are submitted to a wafer plant for circuit fabrication. Patterned circuits are formed on wafers after performing a series of operations including, for example, doping, metal deposition, photolithography and etching processes and dielectric depositions. Thereafter, the wafers are sent to a packaging plant where the wafers are diced up into chips and assembled into individual packages. The chip and the substrate are electrically connected by using wires or bumps. After the packaging process, the chip and the electrical connection between the chip and the substrate are well protected.
FIG. 1 is a schematic cross-sectional view of a conventional wire-bond chip package. As shown in FIG. 1, the backside 112 of a chip 110 is attached to the upper surface 132 of a substrate 130 through silver epoxy 120. The chip 110 and the substrate 130 are electrically connected through a plurality of conductive wires 140. The chip 110 and the conductive wires 140 are completely enclosed by insulating material 150, which also protects the chip 110 and prevents any short-circuit between the conductive wires 140. In addition, a plurality of contacts 160 is directly attached to the bottom surface 134 of the substrate 130. Through the contacts 160, the substrate 130 is able to connect electrically with external circuits. The contacts 160 attached to the bottom surface 134 of the substrate 130 are conductive structures including, for example, solder balls, pins or electrode bumps.
In the aforementioned chip package 100, the average length of each piece of conductive wire 140 is rather long (mostly greater than 130 mil) and its diameter is rather small (mostly smaller than 1.2 mil). Hence, an impedance mismatch between the conductive wires 140 and the circuits inside the chip 110 or substrate 130 is quite common and often results in rapid signal decay. Ultimately, the access signals frequently contain errors. In addition, parasitic inductance/capacitance effect is especially serious when the chip performs a high frequency operation. In the presence of parasitic inductance/capacitance effect, signal reflections inside the chip package will be pervasive.
FIG. 2 is a schematic cross-sectional view of a conventional flip-chip package. The chip 210 is mounted on a top surface 232 of a substrate 230 via bumps 220 and electrically connected with the substrate 230. An insulating material 240 is dispensed between the chip 210 and the substrate 230 and envelops the bumps 220. Contacts 250 are mounted on a bottom surface 234 of the substrate 230 and electrically connect the substrate 230 to external circuits. The contacts 250 are conductive structures, such as, solder balls, pins or electrode bumps.
As shown in FIG. 2, the bumps 220 of the chip package 200 are positioned in a small area on the top surface 232 of the substrate 230 for positioning the chip 110. Hence, a large number of bonding pads 236 must be squeezed within a relatively small area on the top surface 232 of the substrate 230 for contacting with the bumps 220 electrically and mechanically. Furthermore, if the chip 210 has a relatively large surface area, completely filling the space between the chip 210 and the substrate 230 with the insulating material 240 will be difficult. In other words, voids may be created between the chip 210 and the substrate 230 and hence yield of the chip package may be lowered.
As shown in FIGS. 1 and 2, the bonding pads 136, 236 on the substrates 130, 230 for connecting electrically with the respective chips 110, 210 are located on the top surfaces 132, 232. Thus, there is a high concentration of circuits on the top surface 132, 232 of the substrates 130, 230. When these circuits transmit signals, cross talk between circuits will be pervasive. Furthermore, a low cost fabrication method such as lamination cannot be used to fabricate a substrate with high-density circuits. In other words, a built-up fabrication method having a high cost must be employed. Moreover, the bonding pads 136, 236 on the top surfaces 132, 232 of the substrates 130, 230 must connect electrically with the bonding pads 138, 238 on the bottom surfaces 134, 234 of the substrates 130, 230 through conductive vias (not shown). Therefore, signals must pass through the conductive vias in the substrates 130, 230 before arriving at the bottom surfaces 134, 234 of the substrates 130, 230. In other words, the substrate 130, 230 must provide a lot of space to accommodate these vias, rendering any further reduction of substrate areas difficult.